module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 

    wire out_1_a;
    wire out_1_b;
    wire out_2;
    
    assign out_1_a = a && b;
    assign out_1_b = c && d;
    assign out_2 = out_1_a || out_1_b;
    assign out = out_2;
    assign out_n = !out_2;
    
endmodule
